* Schematics Netlist *



C_C1         0 BUF_OUT  {CL}  
M_M14         BUF_IN $N_0001 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M15         Vdd BUF_IN $N_0002 Vdd MbreakP  
+ L={L}  
+ W={WP*(K1)}         
M_M19         $N_0002 BUF_IN 0 0 MbreakN  
+ L={L}  
+ W={WN*(K1)}         
M_M17         Vdd $N_0002 BUF_OUT Vdd MbreakP  
+ L={L}  
+ W={WP*K2}         
M_M21         BUF_OUT $N_0002 0 0 MbreakN  
+ L={L}  
+ W={WN*(K2)}         
M_M30         NAND2_IN $N_0003 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M31         Vdd IN $N_0003 Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M32         Vdd $N_0003 NAND2_IN Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M33         $N_0003 IN 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M20         $N_0001 IN 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M36         Vdd NAND2_OUT $N_0004 Vdd MbreakP  
+ L={L}  
+ W={WP*M}         
M_M37         $N_0004 NAND2_OUT 0 0 MbreakN  
+ L={L}  
+ W={WN*M}         
M_M43         $N_0005 IN 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M41         Vdd IN $N_0005 Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M45         $N_0006 NAND3_OUT 0 0 MbreakN  
+ L={L}  
+ W={WN*M}         
M_M44         Vdd NAND3_OUT $N_0006 Vdd MbreakP  
+ L={L}  
+ W={WP*M}         
M_M13         Vdd $N_0001 BUF_IN Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M22         INV_IN $N_0007 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M25         $N_0007 IN 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M27         INV_OUT INV_IN 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M23         Vdd IN $N_0007 Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M52         Vdd $N_0007 INV_IN Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M53         Vdd INV_IN INV_OUT Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M28         Vdd INV_OUT $N_0008 Vdd Mbreakp  
+ L={L}  
+ W={WP*M}         
M_M29         $N_0008 INV_OUT 0 0 MbreakN  
+ L={L}  
+ W={WN*M}         
M_M57         Vdd Vdd NAND3_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M59         $N_0009 Vdd 0 0 MbreakN  
+ L={L}  
+ W={WN*3}         
M_M34         Vdd NAND2_IN NAND2_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M55         Vdd $N_0010 NAND2_OUT $N_0010 MbreakP  
+ L={L}  
+ W={WP}         
M_M54         $N_0011 $N_0010 0 0 MbreakN  
+ L={L}  
+ W={WN*2}         
M_M35         NAND2_OUT NAND2_IN $N_0011 0 MbreakN  
+ L={L}  
+ W={WN*2}         
M_M58         $N_0012 Vdd $N_0009 0 MbreakN  
+ L={L}  
+ W={WN*3}         
M_M56         Vdd Vdd NAND3_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M48         NAND3_OUT NAND3_IN $N_0012 0 MbreakN  
+ L={L}  
+ W={WN*3}         
M_M42         Vdd $N_0005 NAND3_IN Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M40         NAND3_IN $N_0005 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M1         Vdd IN $N_0001 Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M62         $N_0013 NAND4_OUT 0 0 MbreakN  
+ L={L}  
+ W={WN*M}         
M_M63         Vdd NAND4_OUT $N_0013 Vdd MbreakP  
+ L={L}  
+ W={WP*M}         
M_M64         Vdd Vdd NAND4_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M67         Vdd Vdd NAND4_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M72         Vdd Vdd NAND4_OUT Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M76         $N_0014 Vdd 0 0 MbreakN  
+ L={L}  
+ W={WN*4}         
M_M74         $N_0016 Vdd $N_0015 0 MbreakN  
+ L={L}  
+ W={WN*4}         
M_M75         $N_0015 Vdd $N_0014 0 MbreakN  
+ L={L}  
+ W={WN*4}         
M_M68         NAND4_OUT NAND4_IN $N_0016 0 MbreakN  
+ L={L}  
+ W={WN*4}         
M_M60         $N_0017 IN 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M61         Vdd IN $N_0017 Vdd Mbreakp  
+ L={L}  
+ W={WP}         
M_M70         Vdd $N_0017 NAND4_IN Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M71         NAND4_IN $N_0017 0 0 MbreakN  
+ L={L}  
+ W={WN}         
M_M69         Vdd NAND4_IN NAND4_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
M_M46         Vdd NAND3_IN NAND3_OUT Vdd MbreakP  
+ L={L}  
+ W={WP}         
V_V1         Vdd 0 {VDD}
V_V2         IN 0  
+PULSE 0 2 10n 1n 1n 9n 20n