211 lines
No EOL
3.9 KiB
Text
211 lines
No EOL
3.9 KiB
Text
MICROWIND 1.00
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*
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* Rule File for CMOS 0.25µm
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* Date : 18 Nov 97
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*
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* Status : preliminary
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*
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NAME CMOS 0.25µm - 5 Metal
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*
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lambda = 0.15 (Lambda is set to half the gate size)
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metalLayers = 5 (Number of metal layers : 5)
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*
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* Design rules associated to each layer
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*
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* Well
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r101 = 10 (well width)
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r102 = 11 (well spacing)
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*
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* Diffusion
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*
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r201 = 4 (diffusion width)
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r202 = 4 (diffusion spacing)
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r203 = 6 (border of nwell on diffp)
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r204 = 6 (nwell to next diffn)
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*
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* Poly
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*
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r301 = 2 (poly width)
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r302 = 2 (ngate width)
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r303 = 2 (pgate width)
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r304 = 3 (poly spacing)
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r305 = 1 (spacing poly and unrelated diff)
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r306 = 4 (width of drain and source diff)
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r307 = 2 (extra gate poly)
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* Contact
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r401 = 2 (contact width)
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r402 = 3 (contact spacing)
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r403 = 2 (metal border for contact)
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r404 = 2 (poly border for contact)
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r405 = 2 (diff border for contact)
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* metal
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r501 = 3 (metal width)
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r502 = 3 (metal spacing)
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* via
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r601 = 2 (Via width)
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r602 = 3 (Spacing)
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r604 = 2 (border of metal&metal2)
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* metal 2
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r701 = 4 (Metal 2 width)
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r702 = 4 (spacing)
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* via 2
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r801 = 2 (Via width)
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r802 = 3 (Spacing)
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r804 = 2 (border of metal2&metal3)
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* metal 3
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r901 = 4 (width)
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r902 = 4 (spacing)
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* via 3
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ra01 = 2 (Via width)
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ra02 = 3 (Spacing)
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ra04 = 2 (border of metal3&metal4)
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* metal 4
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rb01 = 4 (width)
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rb02 = 4 (spacing)
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* via 4
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rc01 = 2 (Via width)
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rc02 = 3 (Spacing)
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rc04 = 2 (border of metal4&metal5)
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* metal 5
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rd01 = 4 (width)
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rd02 = 10 (spacing)
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*
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* Passivation nitrideand pad rules
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*
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rp01 = 550 (Pad width)
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rp02 = 550 (Pad spacing)
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rp03 = 25 (Border of Vias)
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rp04 = 25 (Border of metals)
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rp05 = 150 (to unrelated active areas)
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*
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* Thickness of conductors for FEM computing and process aspect
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* All in µm
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*
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thpoly = 0.25
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hepoly = 0.4
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thme = 0.6
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heme = 1.0
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thm2 = 0.6
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hem2 = 2.5
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thm3 = 0.6
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hem3 = 4.0
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thm4 = 0.6
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hem4 = 6.0
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thm5 = 0.6
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hem5 = 7.5
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thpass = 0.5
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hepass = 8.0
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thnit = 0.5
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henit = 8.5
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*
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* Resistances
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* Unit is ohm/square
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*
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repo = 20
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reme = 0.5
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rem2 = 0.1
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rem3 = 0.1
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rem4 = 0.1
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rem5 = 0.1
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*
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*
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* Parasitic capacitances
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*
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cpoOxyde= 4600 (Surface capacitance Poly/Thin oxyde aF/µm2)
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cpobody = 80 (Poly/Body)
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cmebody = 28
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cmelineic = 42
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cmepoly = 60
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cm2body = 13
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cm2lineic = 36
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cm2poly = 16
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cm2metal = 38
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cm3body = 8
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cm3lineic = 33
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cm4body = 6
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cm4lineic = 30
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cm5body = 5
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cm5lineic = 31
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cmelineic = 42
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cgsn = 500 ( Gate/source capa of nMOS)
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cgsp = 500
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*
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* Crosstalk
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*
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cmextk = 52 (Lineic capacitance for crosstalk coupling in aF/µm)
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cm2xtk = 56 (C is computed using Cx=cmextk*l/spacing)
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cm3xtk = 56 (C is computed using Cx=cmextk*l/spacing)
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cm4xtk = 56 (C is computed using Cx=cmextk*l/spacing)
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cm5xtk = 56 (C is computed using Cx=cmextk*l/spacing)
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*
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* Junction capacitances
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*
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cdnpwell = 350 (n+/psub)
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cdpnwell = 300 (p+/nwell)
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cnwell = 250 (nwell/psub)
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cpwell = 100 (pwell/nsub)
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cldn = 300 (Lineic capacitance N+/P- aF/µm)
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cldp = 300 (Idem for P+/N-)
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*
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* Nmos Model 3 parameters
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*
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NMOS
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l3vto = 0.5
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l3vmax = 130e3
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l3gamma = 0.4
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l3theta = 0.3
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l3kappa = 0.01
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l3phi = 0.7
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l3ld = -0.05
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l3kp = 250e-6
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l3nss = 0.07
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l3cgd = 10
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l3cgs = 10
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*
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* Pmos Model 3
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*
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PMOS
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l3vto = -0.5
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l3vmax = 100e3
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l3gamma = 0.4
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l3theta = 0.3
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l3kappa = 0.01
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l3phi = 0.7
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l3ld = -0.05
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l3kp = 70e-6
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l3nss = 0.07
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l3cgd = 10
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l3cgs = 10
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*
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*
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* CIF&GDS2 Layers
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* MicroWind layer, CIF layer, Gds2 layer, overetch
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*
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cif nwell 1 1 0.0
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cif diffp 17 17 0.5
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cif diffn 16 16 0.5
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cif aarea 2 2 0.5
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cif poly 13 13 0.0
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cif contact 19 19 0.0
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cif metal 23 23 0.0
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cif via 25 25 0.0
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cif metal2 27 27 0.0
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cif via2 32 32 0.0
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cif metal3 24 34 0.0
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cif via3 35 35 0.0
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cif metal4 36 36 0.0
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cif via4 52 52 0.0
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cif metal5 53 53 0.0
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cif passiv 31 31 0.0
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cif text 53 53 0.0
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*
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*
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* MicroWind simulation parameters
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*
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deltaT = 2e-12 (Minimum simulation interval dT)
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vdd = 2.5
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temperature = 27
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*
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* End CMOS 0.25 µm
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*
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* |