164 lines
3.9 KiB
Text
164 lines
3.9 KiB
Text
* Schematics Netlist *
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C_C1 0 BUF_OUT {CL}
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M_M14 BUF_IN $N_0001 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M15 Vdd BUF_IN $N_0002 Vdd MbreakP
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+ L={L}
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+ W={WP*(K1)}
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M_M19 $N_0002 BUF_IN 0 0 MbreakN
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+ L={L}
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+ W={WN*(K1)}
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M_M17 Vdd $N_0002 BUF_OUT Vdd MbreakP
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+ L={L}
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+ W={WP*K2}
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M_M21 BUF_OUT $N_0002 0 0 MbreakN
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+ L={L}
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+ W={WN*(K2)}
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M_M30 NAND2_IN $N_0003 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M31 Vdd IN $N_0003 Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M32 Vdd $N_0003 NAND2_IN Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M33 $N_0003 IN 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M20 $N_0001 IN 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M36 Vdd NAND2_OUT $N_0004 Vdd MbreakP
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+ L={L}
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+ W={WP*M}
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M_M37 $N_0004 NAND2_OUT 0 0 MbreakN
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+ L={L}
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+ W={WN*M}
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M_M43 $N_0005 IN 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M41 Vdd IN $N_0005 Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M45 $N_0006 NAND3_OUT 0 0 MbreakN
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+ L={L}
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+ W={WN*M}
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M_M44 Vdd NAND3_OUT $N_0006 Vdd MbreakP
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+ L={L}
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+ W={WP*M}
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M_M13 Vdd $N_0001 BUF_IN Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M22 INV_IN $N_0007 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M25 $N_0007 IN 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M27 INV_OUT INV_IN 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M23 Vdd IN $N_0007 Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M52 Vdd $N_0007 INV_IN Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M53 Vdd INV_IN INV_OUT Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M28 Vdd INV_OUT $N_0008 Vdd Mbreakp
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+ L={L}
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+ W={WP*M}
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M_M29 $N_0008 INV_OUT 0 0 MbreakN
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+ L={L}
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+ W={WN*M}
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M_M57 Vdd Vdd NAND3_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M59 $N_0009 Vdd 0 0 MbreakN
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+ L={L}
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+ W={WN*3}
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M_M34 Vdd NAND2_IN NAND2_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M55 Vdd $N_0010 NAND2_OUT $N_0010 MbreakP
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+ L={L}
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+ W={WP}
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M_M54 $N_0011 $N_0010 0 0 MbreakN
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+ L={L}
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+ W={WN*2}
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M_M35 NAND2_OUT NAND2_IN $N_0011 0 MbreakN
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+ L={L}
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+ W={WN*2}
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M_M58 $N_0012 Vdd $N_0009 0 MbreakN
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+ L={L}
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+ W={WN*3}
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M_M56 Vdd Vdd NAND3_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M48 NAND3_OUT NAND3_IN $N_0012 0 MbreakN
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+ L={L}
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+ W={WN*3}
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M_M42 Vdd $N_0005 NAND3_IN Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M40 NAND3_IN $N_0005 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M1 Vdd IN $N_0001 Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M62 $N_0013 NAND4_OUT 0 0 MbreakN
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+ L={L}
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+ W={WN*M}
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M_M63 Vdd NAND4_OUT $N_0013 Vdd MbreakP
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+ L={L}
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+ W={WP*M}
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M_M64 Vdd Vdd NAND4_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M67 Vdd Vdd NAND4_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M72 Vdd Vdd NAND4_OUT Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M76 $N_0014 Vdd 0 0 MbreakN
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+ L={L}
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+ W={WN*4}
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M_M74 $N_0016 Vdd $N_0015 0 MbreakN
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+ L={L}
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+ W={WN*4}
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M_M75 $N_0015 Vdd $N_0014 0 MbreakN
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+ L={L}
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+ W={WN*4}
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M_M68 NAND4_OUT NAND4_IN $N_0016 0 MbreakN
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+ L={L}
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+ W={WN*4}
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M_M60 $N_0017 IN 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M61 Vdd IN $N_0017 Vdd Mbreakp
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+ L={L}
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+ W={WP}
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M_M70 Vdd $N_0017 NAND4_IN Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M71 NAND4_IN $N_0017 0 0 MbreakN
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+ L={L}
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+ W={WN}
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M_M69 Vdd NAND4_IN NAND4_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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M_M46 Vdd NAND3_IN NAND3_OUT Vdd MbreakP
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+ L={L}
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+ W={WP}
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V_V1 Vdd 0 {VDD}
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V_V2 IN 0
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+PULSE 0 2 10n 1n 1n 9n 20n
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