MIET_counter/analog/params/RING_LOADED.net
2024-03-17 16:01:20 +03:00

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Text

* Schematics Netlist *
V_V3 Vdd 0 {VDD}
M_M53 Vdd $N_0001 $N_0002 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M57 Vdd $N_0003 $N_0004 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M59 Vdd GEN_OUT $N_0005 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M61 Vdd $N_0006 $N_0007 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M63 Vdd $N_0008 $N_0009 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M65 Vdd $N_0010 $N_0011 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M55 Vdd $N_0012 $N_0013 Vdd Mbreakp
+ L={L}
+ W={WP*(M-1)}
M_M54 $N_0002 $N_0001 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
C_C2 0 $N_0001 {CL}
M_M56 $N_0013 $N_0012 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
M_M4 $N_0012 $N_0001 0 0 MbreakN
+ L={L}
+ W={WN}
M_M3 Vdd $N_0001 $N_0012 Vdd Mbreakp
+ L={L}
+ W={WP}
M_M58 $N_0004 $N_0003 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
M_M7 $N_0003 $N_0012 0 0 MbreakN
+ L={L}
+ W={WN}
M_M8 Vdd $N_0012 $N_0003 Vdd MbreakP
+ L={L}
+ W={WP}
M_M60 $N_0005 GEN_OUT 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
M_M9 GEN_OUT $N_0003 0 0 MbreakN
+ L={L}
+ W={WN}
M_M10 Vdd $N_0003 GEN_OUT Vdd MbreakP
+ L={L}
+ W={WP}
M_M62 $N_0007 $N_0006 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
M_M11 $N_0006 GEN_OUT 0 0 MbreakN
+ L={L}
+ W={WN}
M_M12 Vdd GEN_OUT $N_0006 Vdd MbreakP
+ L={L}
+ W={WP}
M_M64 $N_0009 $N_0008 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
M_M13 $N_0008 $N_0006 0 0 MbreakN
+ L={L}
+ W={WN}
M_M14 Vdd $N_0006 $N_0008 Vdd MbreakP
+ L={L}
+ W={WP}
M_M66 $N_0011 $N_0010 0 0 MbreakN
+ L={L}
+ W={WN*(M-1)}
M_M48 Vdd $N_0010 $N_0001 Vdd MbreakP
+ L={L}
+ W={WP}
M_M15 $N_0010 $N_0008 0 0 MbreakN
+ L={L}
+ W={WN}
M_M16 Vdd $N_0008 $N_0010 Vdd MbreakP
+ L={L}
+ W={WP}
M_M47 $N_0001 $N_0010 0 0 MbreakN
+ L={L}
+ W={WN}