d97f0c0757
Boot minos on the real Zynq-7020 PS (Cortex-A9) without Vivado, an FSBL,
a bitstream, or DDR init — loaded straight into on-chip RAM over JTAG.
- link-zynq-ocm.ld: link the ARM build into OCM (0x0, 192 KiB), which is
alive from reset, so no FSBL/ps7_init and no DDR are needed.
- zynq/openocd-zynq.cfg: OpenOCD config for the on-board FT2232H. Its
EEPROM reports a generic 0403:6010 ("Adapt Device"), which Xilinx
hw_server refuses to auto-detect but OpenOCD drives directly; it sees
the full chain (PL boundary-scan 0x23727093 + ARM DAP 0x4ba00477).
- Makefile: 'zynq' builds the OCM ELF; 'run-zynq' halts A9 core0, loads
the image, and resumes.
The one non-obvious step: the on-board boot firmware leaves the core with
MMU + D-cache + I-cache enabled, which shadow the freshly loaded OCM and
make a plain resume run nothing. run-zynq clears SCTLR to 0x08C54C78 and
forces SVC mode before resuming. Halting (not resetting) keeps the
firmware's PS clock setup so the UART stays live.
Verified on hardware: banner once, then live keystroke echo over the
UART console (ttyUSB1 @115200). Same shared C core now boots on real
RISC-V (D1) and real ARM (Zynq) silicon, plus QEMU x86/riscv/arm.
156 lines
5.7 KiB
Makefile
156 lines
5.7 KiB
Makefile
# minos — minimal multi-arch kernel (M1)
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# One clang, three ISAs. Build all in parallel: make -j
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#
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# make build all three (x86, riscv, arm)
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# make x86 build one arch
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# make run-riscv build + boot that arch under QEMU (-nographic; Ctrl-A X to quit)
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# make sizes compare code size across arches
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# make clean
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CC := clang
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LD := ld.lld
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OBJCOPY := llvm-objcopy
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ARCHES := x86 riscv arm
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# Shared flags. Per-arch target/flags below.
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CFLAGS := -ffreestanding -nostdlib -fno-pic -O2 -Wall -Wextra -Iinclude -g -MMD -MP
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COMMON := common/main.c common/console.c
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# --- per-arch knobs -------------------------------------------------------
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x86_TARGET := --target=i386-unknown-none -m32
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x86_LDEMU := elf_i386
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x86_SRC := arch/x86/boot.S arch/x86/arch.c $(COMMON)
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x86_QEMU := qemu-system-i386 -kernel build/x86/minos.elf -nographic
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riscv_TARGET := --target=riscv64-unknown-none-elf -march=rv64imac -mabi=lp64 -mcmodel=medany
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riscv_LDEMU := elf64lriscv
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riscv_SRC := arch/riscv/boot.S arch/riscv/trap.S arch/riscv/arch.c $(COMMON)
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riscv_QEMU := qemu-system-riscv64 -machine virt -bios none -nographic -kernel build/riscv/minos.elf
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arm_TARGET := --target=arm-none-eabi -mcpu=cortex-a9 -marm
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arm_LDEMU := armelf
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arm_SRC := arch/arm/boot.S arch/arm/vectors.S arch/arm/arch.c $(COMMON)
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arm_QEMU := qemu-system-arm -machine xilinx-zynq-a9 -cpu cortex-a9 -nographic -kernel build/arm/minos.elf
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.PHONY: all clean sizes $(ARCHES) $(addprefix run-,$(ARCHES))
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all: $(ARCHES)
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# Generate per-arch build rules.
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define ARCH_rules
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$(1)_OBJS := $$(patsubst %,build/$(1)/%.o,$$(basename $$(notdir $$($(1)_SRC))))
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build/$(1)/%.o: arch/$(1)/%.S | build/$(1)
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$$(CC) $$($(1)_TARGET) $$(CFLAGS) -c $$< -o $$@
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build/$(1)/%.o: arch/$(1)/%.c | build/$(1)
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$$(CC) $$($(1)_TARGET) $$(CFLAGS) -c $$< -o $$@
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build/$(1)/%.o: common/%.c | build/$(1)
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$$(CC) $$($(1)_TARGET) $$(CFLAGS) -c $$< -o $$@
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build/$(1):
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mkdir -p $$@
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build/$(1)/minos.elf: $$($(1)_OBJS) arch/$(1)/link.ld
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$$(LD) -m $$($(1)_LDEMU) -T arch/$(1)/link.ld -nostdlib $$($(1)_OBJS) -o $$@
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@echo " [$(1)] linked -> $$@"
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$(1): build/$(1)/minos.elf
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run-$(1): build/$(1)/minos.elf
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@echo "== booting $(1) (Ctrl-A X to quit) =="
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$$($(1)_QEMU)
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-include $$($(1)_OBJS:.o=.d)
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endef
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$(foreach a,$(ARCHES),$(eval $(call ARCH_rules,$(a))))
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sizes: all
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@echo "arch text+data+bss (bytes)"; \
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for a in $(ARCHES); do \
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printf '%-7s ' $$a; \
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$(OBJCOPY) -O binary build/$$a/minos.elf /tmp/_sz.bin 2>/dev/null; \
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stat -c '%s' /tmp/_sz.bin; \
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done; rm -f /tmp/_sz.bin
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# --- real hardware: Allwinner D1 / Lichee RV via xfel ------------------------
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# Same RISC-V sources, rebuilt with -DBOARD_D1 (UART 0x02500000) and linked
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# for DRAM 0x40000000, emitted as a flat binary xfel can load.
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XFEL ?= xfel
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D1_TARGET := $(riscv_TARGET) -DBOARD_D1
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D1_OBJS := $(patsubst %,build/lichee/%.o,$(basename $(notdir $(riscv_SRC))))
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build/lichee/%.o: arch/riscv/%.S | build/lichee
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$(CC) $(D1_TARGET) $(CFLAGS) -c $< -o $@
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build/lichee/%.o: arch/riscv/%.c | build/lichee
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$(CC) $(D1_TARGET) $(CFLAGS) -c $< -o $@
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build/lichee/%.o: common/%.c | build/lichee
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$(CC) $(D1_TARGET) $(CFLAGS) -c $< -o $@
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build/lichee:
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mkdir -p $@
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build/lichee/minos.elf: $(D1_OBJS) arch/riscv/link-d1.ld
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$(LD) -m $(riscv_LDEMU) -T arch/riscv/link-d1.ld -nostdlib $(D1_OBJS) -o $@
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build/lichee/minos.bin: build/lichee/minos.elf
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$(OBJCOPY) -O binary $< $@
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@echo " [lichee] flat binary -> $@ ($$(stat -c%s $@) bytes)"
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.PHONY: lichee run-lichee
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lichee: build/lichee/minos.bin ## build the D1 flat binary
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# Load & run on the board (must be in FEL mode; needs sudo for USB).
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run-lichee: build/lichee/minos.bin
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@echo "== loading minos onto D1 via xfel =="
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$(XFEL) ddr d1
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$(XFEL) write 0x40000000 build/lichee/minos.bin
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$(XFEL) exec 0x40000000
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@echo "== running. Watch /dev/ttyUSB0 @115200 for output. =="
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# --- real hardware: Zynq-7000 PS (Cortex-A9) via JTAG/OpenOCD ----------------
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# Same ARM sources, re-linked into on-chip RAM (OCM at 0x0) so no FSBL/DDR
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# init is needed. Loaded over JTAG with OpenOCD (the on-board FT2232H is a
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# generic 0403:6010 that Xilinx hw_server won't auto-detect, but OpenOCD does).
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OPENOCD ?= openocd
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OOCD_CFG := zynq/openocd-zynq.cfg
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ZYNQ_OBJS := $(patsubst %,build/zynq/%.o,$(basename $(notdir $(arm_SRC))))
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build/zynq/%.o: arch/arm/%.S | build/zynq
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$(CC) $(arm_TARGET) $(CFLAGS) -c $< -o $@
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build/zynq/%.o: arch/arm/%.c | build/zynq
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$(CC) $(arm_TARGET) $(CFLAGS) -c $< -o $@
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build/zynq/%.o: common/%.c | build/zynq
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$(CC) $(arm_TARGET) $(CFLAGS) -c $< -o $@
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build/zynq:
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mkdir -p $@
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build/zynq/minos.elf: $(ZYNQ_OBJS) arch/arm/link-zynq-ocm.ld
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$(LD) -m $(arm_LDEMU) -T arch/arm/link-zynq-ocm.ld -nostdlib $(ZYNQ_OBJS) -o $@
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@echo " [zynq] OCM ELF -> $@"
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.PHONY: zynq run-zynq
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zynq: build/zynq/minos.elf ## build the Zynq OCM ELF
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# Halt A9 core0, load the ELF into OCM, set PC to _start, resume.
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# Watch the UART console (ttyUSB1 @115200) for output.
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#
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# Critical: the on-board boot firmware leaves the core with MMU + D-cache +
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# I-cache enabled (SCTLR bits 0/2/12). If we resume like that, the stale
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# TLB/cache shadow our freshly loaded OCM and nothing runs. So we clear those
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# bits (SCTLR -> 0x08C54C78) and force SVC mode before resuming. We keep the
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# firmware's PS clock setup (incl. UART) by halting rather than resetting.
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run-zynq: build/zynq/minos.elf
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@echo "== loading minos into Zynq OCM via OpenOCD =="
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$(OPENOCD) -f $(OOCD_CFG) \
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-c "init" \
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-c "targets zynq.cpu0" \
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-c "halt" \
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-c "load_image build/zynq/minos.elf" \
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-c "arm mcr 15 0 1 0 0 0x08C54C78" \
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-c "reg pc 0x00000000" \
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-c "reg cpsr 0x000001d3" \
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-c "resume" \
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-c "shutdown"
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@echo "== running. Watch /dev/ttyUSB1 @115200 for output. =="
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clean:
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rm -rf build
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