minos/arch/arm/link.ld
auser 8c44d12357 minos M1: minimal multi-arch kernel (x86 + RISC-V + ARM/Zynq)
Boots under QEMU on all three ISAs from one clang build:
- shared C core (kmain, console) calls a small per-arch contract (arch.h)
- per-arch asm entry + trap/vector table + UART driver
- parallel Makefile (make -j), 'make run-<arch>', 'make sizes'
M1 = boot, UART up, trap vector installed, banner from kmain().
2026-09-25 00:41:24 +03:00

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/* link.ld (ARM, Zynq-7000) — DDR starts at 0x00000000 on Zynq. QEMU
* xilinx-zynq-a9 loads the -kernel image; place us at a safe low DDR
* address above the vector/OCM region used by the model. */
OUTPUT_FORMAT(elf32-littlearm)
ENTRY(_start)
SECTIONS
{
. = 0x00100000; /* 1 MiB into DDR */
.text : {
KEEP(*(.text.boot))
*(.text .text.*)
}
.rodata : { *(.rodata .rodata.*) }
.data : { *(.data .data.*) }
. = ALIGN(8);
__bss_start = .;
.bss : { *(.bss .bss.*) *(COMMON) }
. = ALIGN(8);
__bss_end = .;
. = ALIGN(16);
. += 0x4000; /* 16 KiB stack */
_stack_top = .;
}