8c44d12357
Boots under QEMU on all three ISAs from one clang build: - shared C core (kmain, console) calls a small per-arch contract (arch.h) - per-arch asm entry + trap/vector table + UART driver - parallel Makefile (make -j), 'make run-<arch>', 'make sizes' M1 = boot, UART up, trap vector installed, banner from kmain().
65 lines
2.7 KiB
Markdown
65 lines
2.7 KiB
Markdown
# minos — a minimal multi-arch kernel
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One tiny OS core, three ISAs: **x86 (i386)**, **RISC-V (rv64)**, **ARM
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(Cortex-A9 / Zynq-7000)**. Built by a single `clang` in parallel so you can
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compare how the same C behaves across architectures.
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Milestone **M1** (this state): each target boots, brings up its UART, sets its
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interrupt/trap vector, and prints a banner from shared C (`kmain`).
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## Design
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The only boundary is a small per-arch **contract** (`include/arch.h`):
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```
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arch_early_init() bring up the UART
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arch_uart_putc(c) emit one byte
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arch_set_trap_vector() install IDT / mtvec / VBAR
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arch_name() banner string
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arch_halt() hlt / wfi
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```
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Everything in `common/` is portable C and calls only that contract. Each
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`arch/<name>/` supplies the irreducible assembly (`boot.S`, trap/vector table)
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plus a C file implementing the contract and a linker script.
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```
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common/ main.c (kmain), console.c (putc/puts/puthex)
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include/ arch.h (the contract), console.h
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arch/x86/ boot.S (multiboot) arch.c (COM1 0x3F8, IDT) link.ld (1 MiB)
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arch/riscv/ boot.S (_start) trap.S (mtvec) arch.c (UART 0x10000000)
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arch/arm/ boot.S (_start) vectors.S (VBAR) arch.c (Cadence UART 0xE0000000)
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```
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## Build & run
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```sh
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make -j # build all three in parallel
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make run-x86 # boot under QEMU (Ctrl-A X to quit)
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make run-riscv
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make run-arm
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make sizes # compare stripped binary size
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make clean
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```
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## The interesting comparison (M1)
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| Aspect | x86 (i386) | RISC-V (rv64) | ARM (Cortex-A9) |
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|-------------------|-------------------------|-----------------------|--------------------------|
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| Entry protocol | Multiboot1 header | `_start` @ 0x80000000 | `_start` @ DDR |
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| Console | port I/O `outb` 0x3F8 | MMIO 16550 0x10000000 | MMIO Cadence 0xE0000000 |
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| Trap vector | IDT via `lidt` | `mtvec` CSR | `VBAR` (CP15) |
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| Multi-core gate | (single by default) | `mhartid` check | `MPIDR` check |
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| Halt | `hlt` | `wfi` | `wfi` |
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| Idle byte size | ~890 | ~816 | ~800 |
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## Real hardware (next)
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- **RISC-V**: the only change is the UART base — `0x10000000` (QEMU virt) →
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`0x02500000` (Allwinner D1 / Lichee RV). Loadable via `xfel`.
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- **ARM/Zynq**: same Cadence UART base as the real PS; boot via U-Boot/JTAG.
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- **x86**: boot the multiboot ELF from GRUB.
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## Roadmap
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- **M2**: real trap handlers + a timer tick per arch.
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- **M3**: expose a tiny syscall-style interface (the "own interface").
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