775a02cf3f
Bring up minos on the Allwinner D1 (Lichee RV) over FEL/xfel and add bidirectional UART so the console can read keystrokes, not just print. D1 / Lichee RV boot: - riscv arch.c: select UART0 base by -DBOARD_D1 (0x02500000 vs QEMU 0x10000000) and add a reg-shift abstraction (uart_rd/uart_wr): the D1's Synopsys DW-8250 uses 32-bit registers at 4-byte spacing, which is what made the first hardware boot silent. - d1_uart0_init(): gate/deassert UART0 clock, mux PB8/PB9 to UART0, set 115200 8N1, clear FIFOs, force non-loopback, drain stale RX. - link-d1.ld: link for DRAM at 0x40000000 (xfel exec target, M-mode). - Makefile: 'lichee' builds the flat binary; 'run-lichee' loads it via xfel (ddr d1 / write / exec). - arch_name() reports the concrete board. UART input (all archs): - arch contract gains arch_uart_getc() and arch_uart_rx_ready(), implemented for riscv, x86 (COM1) and arm (Cadence UART). - console gains getc() and drain_rx(). - kmain() runs an interactive echo loop (seed of the M3 console). Verified: echo works under QEMU on x86/riscv/arm, and on real D1 hardware (banner once, then live keystroke echo over UART0 @115200).
31 lines
790 B
Text
31 lines
790 B
Text
/* link-d1.ld (RISC-V, Allwinner D1 / Lichee RV) — bare-metal via xfel.
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*
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* The D1 boot ROM (FEL) leaves us free to load into DRAM. xfel initialises
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* DRAM ('xfel ddr d1') then writes/execs at 0x40000000 (start of the 512MB+
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* DDR). 'xfel exec' jumps here still in M-mode, which is what minos expects.
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* (QEMU 'virt' uses 0x80000000 instead — see link.ld.) */
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x40000000; /* DRAM base on D1 */
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.text : {
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KEEP(*(.text.boot)) /* _start must be first */
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*(.text .text.*)
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}
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.rodata : { *(.rodata .rodata.*) }
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.data : { *(.data .data.*) }
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. = ALIGN(8);
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__bss_start = .;
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.bss : { *(.bss .bss.*) *(COMMON) }
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. = ALIGN(8);
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__bss_end = .;
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. = ALIGN(16);
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. += 0x4000; /* 16 KiB boot stack */
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_stack_top = .;
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}
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