Add D1/Lichee RV hardware boot and UART input
Bring up minos on the Allwinner D1 (Lichee RV) over FEL/xfel and add bidirectional UART so the console can read keystrokes, not just print. D1 / Lichee RV boot: - riscv arch.c: select UART0 base by -DBOARD_D1 (0x02500000 vs QEMU 0x10000000) and add a reg-shift abstraction (uart_rd/uart_wr): the D1's Synopsys DW-8250 uses 32-bit registers at 4-byte spacing, which is what made the first hardware boot silent. - d1_uart0_init(): gate/deassert UART0 clock, mux PB8/PB9 to UART0, set 115200 8N1, clear FIFOs, force non-loopback, drain stale RX. - link-d1.ld: link for DRAM at 0x40000000 (xfel exec target, M-mode). - Makefile: 'lichee' builds the flat binary; 'run-lichee' loads it via xfel (ddr d1 / write / exec). - arch_name() reports the concrete board. UART input (all archs): - arch contract gains arch_uart_getc() and arch_uart_rx_ready(), implemented for riscv, x86 (COM1) and arm (Cadence UART). - console gains getc() and drain_rx(). - kmain() runs an interactive echo loop (seed of the M3 console). Verified: echo works under QEMU on x86/riscv/arm, and on real D1 hardware (banner once, then live keystroke echo over UART0 @115200).
This commit is contained in:
Шурупов Илья Викторович
parent
59a433f949
commit
775a02cf3f
9 changed files with 250 additions and 10 deletions
33
Makefile
33
Makefile
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@ -73,5 +73,38 @@ sizes: all
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stat -c '%s' /tmp/_sz.bin; \
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done; rm -f /tmp/_sz.bin
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# --- real hardware: Allwinner D1 / Lichee RV via xfel ------------------------
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# Same RISC-V sources, rebuilt with -DBOARD_D1 (UART 0x02500000) and linked
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# for DRAM 0x40000000, emitted as a flat binary xfel can load.
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XFEL ?= xfel
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D1_TARGET := $(riscv_TARGET) -DBOARD_D1
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D1_OBJS := $(patsubst %,build/lichee/%.o,$(basename $(notdir $(riscv_SRC))))
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build/lichee/%.o: arch/riscv/%.S | build/lichee
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$(CC) $(D1_TARGET) $(CFLAGS) -c $< -o $@
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build/lichee/%.o: arch/riscv/%.c | build/lichee
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$(CC) $(D1_TARGET) $(CFLAGS) -c $< -o $@
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build/lichee/%.o: common/%.c | build/lichee
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$(CC) $(D1_TARGET) $(CFLAGS) -c $< -o $@
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build/lichee:
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mkdir -p $@
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build/lichee/minos.elf: $(D1_OBJS) arch/riscv/link-d1.ld
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$(LD) -m $(riscv_LDEMU) -T arch/riscv/link-d1.ld -nostdlib $(D1_OBJS) -o $@
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build/lichee/minos.bin: build/lichee/minos.elf
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$(OBJCOPY) -O binary $< $@
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@echo " [lichee] flat binary -> $@ ($$(stat -c%s $@) bytes)"
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.PHONY: lichee run-lichee
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lichee: build/lichee/minos.bin ## build the D1 flat binary
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# Load & run on the board (must be in FEL mode; needs sudo for USB).
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run-lichee: build/lichee/minos.bin
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@echo "== loading minos onto D1 via xfel =="
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$(XFEL) ddr d1
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$(XFEL) write 0x40000000 build/lichee/minos.bin
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$(XFEL) exec 0x40000000
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@echo "== running. Watch /dev/ttyUSB0 @115200 for output. =="
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clean:
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rm -rf build
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@ -10,7 +10,8 @@
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#define UART_MR 0x04 /* mode register */
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#define UART_SR 0x2C /* channel status register */
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#define UART_FIFO 0x30 /* tx/rx FIFO */
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#define UART_SR_TXFULL (1u << 4)
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#define UART_SR_TXFULL (1u << 4)
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#define UART_SR_RXEMPTY (1u << 1)
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/* Control register bits */
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#define CR_RXRES (1u << 0) /* RX logic reset */
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@ -39,6 +40,18 @@ void arch_uart_putc(char c)
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*reg(UART_FIFO) = (unsigned int)(unsigned char)c;
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}
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char arch_uart_getc(void)
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{
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while (*reg(UART_SR) & UART_SR_RXEMPTY) /* wait for a received byte */
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;
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return (char)(*reg(UART_FIFO) & 0xff);
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}
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int arch_uart_rx_ready(void)
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{
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return (*reg(UART_SR) & UART_SR_RXEMPTY) ? 0 : 1;
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}
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/* M1: point the vector base (VBAR) at our table (defined in vectors.S). */
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extern void vector_table(void);
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void arch_set_trap_vector(void)
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@ -6,24 +6,130 @@
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#include "arch.h"
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#include "console.h"
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/* UART base differs by platform. Both are 16550-compatible, so the same
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* driver works; only the MMIO base changes.
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* QEMU 'virt' : 0x10000000
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* Allwinner D1 (Lichee RV) UART0 : 0x02500000
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* Select with -DBOARD_D1 at build time (see 'make lichee'). */
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#ifdef BOARD_D1
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#define UART0_BASE 0x02500000UL
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#else
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#define UART0_BASE 0x10000000UL
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#define UART_THR 0x00 /* transmit holding register */
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#define UART_LSR 0x05 /* line status register */
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#endif
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/* Register numbers (16550). The BYTE offset depends on the platform's
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* register spacing:
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* QEMU 'virt' : 8-bit registers, 1-byte spacing (reg-shift 0)
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* Allwinner D1: Synopsys DW 8250, 32-bit registers, 4-byte spacing
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* (reg-shift 2) — this is the difference that made the
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* first hardware boot silent. */
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#define UART_RBR 0 /* receive buffer register (read) */
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#define UART_THR 0 /* transmit holding register (write) */
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#define UART_LSR 5 /* line status register */
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#define UART_LSR_DR 0x01 /* data ready (RX byte available) */
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#define UART_LSR_THRE 0x20 /* THR empty */
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static volatile unsigned char *const uart =
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(volatile unsigned char *)UART0_BASE;
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#ifdef BOARD_D1
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#define UART_SHIFT 2
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static inline unsigned int uart_rd(int reg)
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{
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return *(volatile unsigned int *)(UART0_BASE + ((unsigned long)reg << UART_SHIFT));
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}
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static inline void uart_wr(int reg, unsigned int v)
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{
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*(volatile unsigned int *)(UART0_BASE + ((unsigned long)reg << UART_SHIFT)) = v;
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}
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#else
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static inline unsigned int uart_rd(int reg)
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{
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return *(volatile unsigned char *)(UART0_BASE + reg);
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}
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static inline void uart_wr(int reg, unsigned int v)
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{
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*(volatile unsigned char *)(UART0_BASE + reg) = (unsigned char)v;
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}
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#endif
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#ifdef BOARD_D1
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/* Full UART0 bring-up on the Allwinner D1 (sun20i). The FEL boot ROM does
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* NOT guarantee UART0 is clocked/muxed/baud-set, so we do it ourselves.
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* Register map from the D1 user manual. */
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#define CCU_BASE 0x02001000UL
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#define CCU_UART_BGR (CCU_BASE + 0x090C) /* UART bus gating & reset */
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#define PIO_BASE 0x02000000UL
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#define PB_CFG1 (PIO_BASE + 0x0034) /* port B, pins 8..15, 4 bits each */
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#define w32(a, v) (*(volatile unsigned int *)(a) = (unsigned int)(v))
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#define r32(a) (*(volatile unsigned int *)(a))
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/* DW-8250 register numbers (reg-shift 2 applied by uart_wr/uart_rd). */
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#define UART_DLL 0 /* divisor low (DLAB=1) */
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#define UART_DLH 1 /* divisor high (DLAB=1) */
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#define UART_FCR 2 /* FIFO control (write) */
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#define UART_LCR 3 /* line control */
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#define UART_MCR 4 /* modem control */
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#define UART_MCR_LOOP 0x10 /* internal loopback (TX->RX) */
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static void d1_uart0_init(void)
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{
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unsigned int v;
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/* 1. Enable UART0: bus gate (bit0) + deassert reset (bit16). */
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v = r32(CCU_UART_BGR);
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v |= (1u << 16) | (1u << 0);
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w32(CCU_UART_BGR, v);
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/* 2. Mux PB8=UART0_TX, PB9=UART0_RX to function 6. */
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v = r32(PB_CFG1);
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v &= ~0xFFu; /* clear PB8 [3:0] and PB9 [7:4] */
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v |= (6u << 0) | (6u << 4);
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w32(PB_CFG1, v);
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/* 3. Program 115200 8N1. UART src = 24 MHz OSC ->
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* divisor = 24000000 / (16 * 115200) ~= 13. */
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uart_wr(UART_LCR, 0x80); /* DLAB = 1 */
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uart_wr(UART_DLL, 13);
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uart_wr(UART_DLH, 0);
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uart_wr(UART_LCR, 0x03); /* 8N1, DLAB = 0 */
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uart_wr(UART_FCR, 0x07); /* enable + clear RX/TX FIFOs */
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/* Defensive: force normal (non-loopback) operation in case the boot
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* ROM left the modem-control internal-loopback bit set, which would
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* feed TX straight back into RX. */
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uart_wr(UART_MCR, 0x00);
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/* Drain any stale bytes sitting in the RX FIFO so the first getc()
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* waits for a real keypress instead of returning garbage. */
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while (uart_rd(UART_LSR) & UART_LSR_DR)
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(void)uart_rd(UART_RBR);
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}
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#endif
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void arch_early_init(void)
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{
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/* QEMU's UART is usable from reset; nothing to do. */
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#ifdef BOARD_D1
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d1_uart0_init();
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#endif
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/* QEMU's UART is usable from reset; nothing to do there. */
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}
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void arch_uart_putc(char c)
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{
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while ((uart[UART_LSR] & UART_LSR_THRE) == 0)
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while ((uart_rd(UART_LSR) & UART_LSR_THRE) == 0)
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;
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uart[UART_THR] = (unsigned char)c;
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uart_wr(UART_THR, (unsigned char)c);
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}
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char arch_uart_getc(void)
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{
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while ((uart_rd(UART_LSR) & UART_LSR_DR) == 0)
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;
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return (char)(uart_rd(UART_RBR) & 0xff);
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}
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int arch_uart_rx_ready(void)
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{
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return (uart_rd(UART_LSR) & UART_LSR_DR) ? 1 : 0;
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}
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/* M1: install a minimal machine trap vector (defined in trap.S). */
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@ -37,7 +143,11 @@ void arch_set_trap_vector(void)
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const char *arch_name(void)
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{
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return "riscv64 (rv64imac)";
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#ifdef BOARD_D1
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return "riscv64 (Allwinner D1 / Lichee RV)";
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#else
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return "riscv64 (rv64imac, QEMU virt)";
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#endif
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}
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const char *arch_cpu_mode(void)
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31
arch/riscv/link-d1.ld
Normal file
31
arch/riscv/link-d1.ld
Normal file
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@ -0,0 +1,31 @@
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/* link-d1.ld (RISC-V, Allwinner D1 / Lichee RV) — bare-metal via xfel.
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*
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* The D1 boot ROM (FEL) leaves us free to load into DRAM. xfel initialises
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* DRAM ('xfel ddr d1') then writes/execs at 0x40000000 (start of the 512MB+
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* DDR). 'xfel exec' jumps here still in M-mode, which is what minos expects.
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* (QEMU 'virt' uses 0x80000000 instead — see link.ld.) */
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OUTPUT_ARCH(riscv)
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ENTRY(_start)
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SECTIONS
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{
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. = 0x40000000; /* DRAM base on D1 */
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.text : {
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KEEP(*(.text.boot)) /* _start must be first */
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*(.text .text.*)
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}
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.rodata : { *(.rodata .rodata.*) }
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.data : { *(.data .data.*) }
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. = ALIGN(8);
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__bss_start = .;
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.bss : { *(.bss .bss.*) *(COMMON) }
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. = ALIGN(8);
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__bss_end = .;
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. = ALIGN(16);
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. += 0x4000; /* 16 KiB boot stack */
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_stack_top = .;
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}
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@ -36,6 +36,18 @@ void arch_uart_putc(char c)
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outb(COM1, (unsigned char)c);
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}
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char arch_uart_getc(void)
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{
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while ((inb(COM1 + 5) & 0x01) == 0) /* wait RX data ready (LSR.DR) */
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;
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return (char)inb(COM1); /* read RBR */
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}
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int arch_uart_rx_ready(void)
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{
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return (inb(COM1 + 5) & 0x01) ? 1 : 0;
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}
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/* M1: minimal IDT. We load a valid-but-empty IDT so the CPU has a
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* table; M2 will fill gates and handle the timer (IRQ0). */
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struct idt_entry {
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@ -16,6 +16,21 @@ void puts(const char *s)
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putc(*s++);
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}
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/* Read one byte from the UART. Portable wrapper over arch_uart_getc(). */
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char getc(void)
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{
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return arch_uart_getc();
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}
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/* Discard any bytes currently waiting in the RX FIFO. Used to drop the
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* bytes our own TX echoes back on half-duplex-wired boards before we start
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* reading real keystrokes. */
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void drain_rx(void)
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{
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while (arch_uart_rx_ready())
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(void)arch_uart_getc();
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}
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/* Minimal unsigned hex printer — enough to show addresses/registers. */
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void puthex(unsigned long v)
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{
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puts("========================================\n");
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puts("hello from kmain()\n");
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arch_halt();
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/* Interactive echo: proves UART input (RX) works. Type on the serial
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* console and minos echoes each key back. This is the seed of a real
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* console — M3 will turn it into a command interface. */
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puts("\nType something (keys are echoed back):\n> ");
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drain_rx(); /* drop any bytes already sitting in the RX FIFO */
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for (;;) {
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char c = getc();
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if (c == '\r' || c == '\n') {
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puts("\n> "); /* newline + fresh prompt */
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continue;
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}
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if (c == 0x7f || c == 0x08) { /* DEL / backspace */
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puts("\b \b");
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continue;
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}
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putc(c); /* echo the key */
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}
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}
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* common/console.c builds print()/puts() on top of just this. */
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void arch_uart_putc(char c);
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/* Blocking read of one byte from the debug UART (polls the RX FIFO).
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* The UART is full-duplex, so this is the mirror of arch_uart_putc. */
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char arch_uart_getc(void);
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/* Non-blocking: return 1 if a received byte is waiting, else 0. Lets the
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* console drain any stale/echoed RX bytes without blocking. */
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int arch_uart_rx_ready(void);
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/* Install the interrupt/trap vector table (IDT / mtvec / VBAR).
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* M1 stubs this; M2 makes it handle a timer tick. */
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void arch_set_trap_vector(void);
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@ -4,5 +4,7 @@
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void putc(char c);
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void puts(const char *s);
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void puthex(unsigned long v);
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char getc(void);
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void drain_rx(void);
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#endif
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