775a02cf3f
Bring up minos on the Allwinner D1 (Lichee RV) over FEL/xfel and add bidirectional UART so the console can read keystrokes, not just print. D1 / Lichee RV boot: - riscv arch.c: select UART0 base by -DBOARD_D1 (0x02500000 vs QEMU 0x10000000) and add a reg-shift abstraction (uart_rd/uart_wr): the D1's Synopsys DW-8250 uses 32-bit registers at 4-byte spacing, which is what made the first hardware boot silent. - d1_uart0_init(): gate/deassert UART0 clock, mux PB8/PB9 to UART0, set 115200 8N1, clear FIFOs, force non-loopback, drain stale RX. - link-d1.ld: link for DRAM at 0x40000000 (xfel exec target, M-mode). - Makefile: 'lichee' builds the flat binary; 'run-lichee' loads it via xfel (ddr d1 / write / exec). - arch_name() reports the concrete board. UART input (all archs): - arch contract gains arch_uart_getc() and arch_uart_rx_ready(), implemented for riscv, x86 (COM1) and arm (Cadence UART). - console gains getc() and drain_rx(). - kmain() runs an interactive echo loop (seed of the M3 console). Verified: echo works under QEMU on x86/riscv/arm, and on real D1 hardware (banner once, then live keystroke echo over UART0 @115200).
93 lines
2.1 KiB
C
93 lines
2.1 KiB
C
/* arch/x86/arch.c — i386 implementation of the arch contract.
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* Uses the legacy 16550 UART on COM1 (port 0x3F8), which QEMU wires to
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* the -nographic serial. Port-mapped I/O — the CISC flavor. */
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#include "arch.h"
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#include "console.h"
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#define COM1 0x3F8
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static inline void outb(unsigned short port, unsigned char val)
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{
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__asm__ volatile("outb %0, %1" :: "a"(val), "Nd"(port));
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}
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static inline unsigned char inb(unsigned short port)
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{
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unsigned char r;
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__asm__ volatile("inb %1, %0" : "=a"(r) : "Nd"(port));
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return r;
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}
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void arch_early_init(void)
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{
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/* Program COM1: 115200 8N1, FIFO on. */
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outb(COM1 + 1, 0x00); /* disable interrupts */
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outb(COM1 + 3, 0x80); /* DLAB on */
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outb(COM1 + 0, 0x01); /* divisor lo -> 115200 */
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outb(COM1 + 1, 0x00); /* divisor hi */
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outb(COM1 + 3, 0x03); /* 8N1, DLAB off */
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outb(COM1 + 2, 0xC7); /* enable+clear FIFO */
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outb(COM1 + 4, 0x0B); /* RTS/DSR set */
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}
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void arch_uart_putc(char c)
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{
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while ((inb(COM1 + 5) & 0x20) == 0) /* wait THR empty */
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;
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outb(COM1, (unsigned char)c);
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}
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char arch_uart_getc(void)
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{
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while ((inb(COM1 + 5) & 0x01) == 0) /* wait RX data ready (LSR.DR) */
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;
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return (char)inb(COM1); /* read RBR */
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}
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int arch_uart_rx_ready(void)
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{
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return (inb(COM1 + 5) & 0x01) ? 1 : 0;
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}
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/* M1: minimal IDT. We load a valid-but-empty IDT so the CPU has a
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* table; M2 will fill gates and handle the timer (IRQ0). */
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struct idt_entry {
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unsigned short off_lo, sel;
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unsigned char zero, flags;
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unsigned short off_hi;
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} __attribute__((packed));
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struct idt_ptr {
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unsigned short limit;
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unsigned int base;
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} __attribute__((packed));
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static struct idt_entry idt[256];
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void arch_set_trap_vector(void)
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{
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struct idt_ptr ptr = { sizeof(idt) - 1, (unsigned int)(unsigned long)idt };
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__asm__ volatile("lidt %0" :: "m"(ptr));
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}
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const char *arch_name(void)
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{
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return "x86 (i386, multiboot)";
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}
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const char *arch_cpu_mode(void)
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{
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/* CPL = low 2 bits of CS. 0 = ring0 (kernel), 3 = ring3 (user). */
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unsigned short cs;
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__asm__ volatile("mov %%cs, %0" : "=r"(cs));
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switch (cs & 3) {
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case 0: return "ring0";
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case 3: return "ring3";
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default: return "ring?";
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}
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}
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void arch_halt(void)
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{
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for (;;)
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__asm__ volatile("hlt");
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}
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