Boot minos on the real Zynq-7020 PS (Cortex-A9) without Vivado, an FSBL,
a bitstream, or DDR init — loaded straight into on-chip RAM over JTAG.
- link-zynq-ocm.ld: link the ARM build into OCM (0x0, 192 KiB), which is
alive from reset, so no FSBL/ps7_init and no DDR are needed.
- zynq/openocd-zynq.cfg: OpenOCD config for the on-board FT2232H. Its
EEPROM reports a generic 0403:6010 ("Adapt Device"), which Xilinx
hw_server refuses to auto-detect but OpenOCD drives directly; it sees
the full chain (PL boundary-scan 0x23727093 + ARM DAP 0x4ba00477).
- Makefile: 'zynq' builds the OCM ELF; 'run-zynq' halts A9 core0, loads
the image, and resumes.
The one non-obvious step: the on-board boot firmware leaves the core with
MMU + D-cache + I-cache enabled, which shadow the freshly loaded OCM and
make a plain resume run nothing. run-zynq clears SCTLR to 0x08C54C78 and
forces SVC mode before resuming. Halting (not resetting) keeps the
firmware's PS clock setup so the UART stays live.
Verified on hardware: banner once, then live keystroke echo over the
UART console (ttyUSB1 @115200). Same shared C core now boots on real
RISC-V (D1) and real ARM (Zynq) silicon, plus QEMU x86/riscv/arm.
Bring up minos on the Allwinner D1 (Lichee RV) over FEL/xfel and add
bidirectional UART so the console can read keystrokes, not just print.
D1 / Lichee RV boot:
- riscv arch.c: select UART0 base by -DBOARD_D1 (0x02500000 vs QEMU
0x10000000) and add a reg-shift abstraction (uart_rd/uart_wr): the D1's
Synopsys DW-8250 uses 32-bit registers at 4-byte spacing, which is what
made the first hardware boot silent.
- d1_uart0_init(): gate/deassert UART0 clock, mux PB8/PB9 to UART0, set
115200 8N1, clear FIFOs, force non-loopback, drain stale RX.
- link-d1.ld: link for DRAM at 0x40000000 (xfel exec target, M-mode).
- Makefile: 'lichee' builds the flat binary; 'run-lichee' loads it via
xfel (ddr d1 / write / exec).
- arch_name() reports the concrete board.
UART input (all archs):
- arch contract gains arch_uart_getc() and arch_uart_rx_ready(),
implemented for riscv, x86 (COM1) and arm (Cadence UART).
- console gains getc() and drain_rx().
- kmain() runs an interactive echo loop (seed of the M3 console).
Verified: echo works under QEMU on x86/riscv/arm, and on real D1
hardware (banner once, then live keystroke echo over UART0 @115200).
Adds arch_cpu_mode() to the contract, reading real hardware state:
x86 CS.CPL -> ring0, RISC-V mhartid (M-only CSR) -> M-mode,
ARM CPSR[4:0] -> SVC. Confirms M1 runs fully privileged, no user mode.
